FIG. 1 illustrates an output buffer circuit 40 for reducing switching induced noise described in the Jeffrey B. Davis U.S. Pat. No. 4,961,010. FIG. 1 corresponds with FIG. 4 of that patent. A relatively large current carrying capacity NMOS transistor element N3 sinks discharge current from the output V.sub.OUT to the low potential power rail GND. N3 is the primary pulldown transistor element for establishing a logic low potential level signal at the output. A relatively large current carrying capacity PMOS transistor element P3 sources charging current from the high potential power rail V.sub.CC to the output V.sub.OUT. P3 is the primary pullup transistor element for establishing a logic high potential level signal at the output. In this example, the output buffer 40 is a non-inverting tristate output device and data signals of logic high and low potential levels propagate from the data signal input V.sub.IN to the output V.sub.OUT after signal propagation delay. The tristate output enable and disable signals are applied at the OE terminal input.
A data signal at the input V.sub.IN passes through two inverting current amplification stages 12,14 and then is applied with the same polarity as at the input to NAND gate 15 and NOR gate 16. NAND gate 15 ultimately drives the primary pullup transistor element P3. NOR gate 16 ultimately drives the primary pulldown transistor element N3. The second input to each of the logic gates 15,16 is derived from the OE terminal input.
An output enable signal OE is applied with inverted polarity OE at the tristate OE terminal. This tristate signal passes through first and second inverting current amplification stages 18,20 and is applied at the same polarity as the OE signal to the input of NOR gate 16. The tristate signal also passes through first and second inverting stages 18,20 and a third inverter stage 22 before it is applied to the input of NAND gate 15. The tristate signal applied to the input of NAND gate 15 is thus of opposite polarity from the OE signal and is in phase with the output enable signal OE.
The logic gate arrangement of the output buffer 40 of FIG. 1 delivers output data signals of logic high and low potential levels at the output V.sub.OUT in phase with data signals at the input V.sub.IN during bistate operation when the output enable signal OE is high (OE low). When the OE signal is low (OE high) during the high impedance third state, the output transistor elements including primary pullup transistor element P3 and primary pulldown transistor element N3 are disabled. The tristate mode at output V.sub.OUT appears as a high impedance to other output buffers on a common bus.
According to the improvements of U.S. Pat. No. 4,961,010, edge rate control circuits are incorporated in the output buffer circuit 40 for controlling turn on of the output pullup and pulldown transistor elements. A relatively small current carrying capacity PMOS secondary pullup transistor element P1 is coupled in parallel with the primary pullup transistor element P3. A relatively small current carrying capacity NMOS secondary pulldown transistor element N1 is coupled in parallel with the primary pulldown transistor element N3. The ratio of current carrying capacities of the primary to secondary pulldown transistor elements N3/N1 and of the primary to secondary pullup transistor elements P3/P1 is preferably at least 4 to 1 or greater and typically in the range of 4/1 to 7/1. For MOS transistors, the current carrying capacity is a function, among other things, of the channel resistance, and in turn the channel width. By way of example a typical channel width for the primary output transistor elements is in the range of 800.mu.-1400.mu.(microns) while the channel width of the secondary output transistor element may be for example 200.mu..
Resistor RD1 is coupled between the control gate nodes of the secondary and primary pulldown transistor elements. Resistor RD1 provides a time constant delay between early turn on of the secondary pulldown transistor element N1 and later turn on of the primary pulldown transistor element N3. Resistor element RD2 is coupled between the control gate nodes of the secondary and primary pullup transistor elements. Resistor RD2 provides a time constant delay between early turn on of the secondary pullup transistor element P1 and later turn on of the primary pullup transistor element P3. Typical resistor values for RD1 and RD2 are 5K ohms and 1K ohms respectively.
The early turn on of small current carrying capacity secondary pulldown transistor element N1 initiates sinking of current from the output V.sub.OUT at only a small current sinking level. The initial sinking current level and the charge acceleration are constrained by the size and internal resistance of the small current carrying capacity transistor element N1. The positive ground rise of potential or ground bounce is proportional to L di/dt, where L is the parasitic inductance LG of the ground lead. This first ground bounce event is constrained to a lower level, typically less than one-half that of the ground bounce peak amplitude for conventional output buffer circuits.
The delay resistor RD1 and the parasitic capacitance of the primary pulldown transistor element N3 form an RC delay network which delays turn on of N3. Upon turn on of the large current carrying capacity primary pulldown transistor element N3, a second positive ground rise of potential occurs. However, the second ground bounce is now limited by the reduction in charge in the output load capacitance and is also reduced to half the conventional ground bounce peak amplitude.
U.S. Pat. No. 4,961,010 provides similar edge rate control measures for reducing noise on the supply rail side of the output buffer circuit. The secondary pullup transistor element P1 initiates a relatively small charging current from the supply rail V.sub.CC to the output V.sub.OUT before turn on of the relatively large charging current of the primary pullup transistor element P3. As a result, first and second V.sub.CC droop spikes are generated and limited to a magnitude typically less than half that of conventional output buffer circuits.
According to typical component values for the circuit of FIG. 1, edge control by sequential turn on of the secondary and then the primary output transistors, with passive delay resistors RD1, RD2, increases signal propagation delay by, for example, 1.5 ns operating into a standard output load capacitance of 50 pf. The additional delay of 1.5 ns increases the typical basic output buffer circuit propagation delay from, for example, 4 ns to 5.5 ns. For rapid turn off of the primary output transistor elements N3, P3 without the edge control and without additional delay during respective opposite transitions at the output, pulldown and pullup delay bypass circuits incorporating bypass transistor elements N2, P2 are provided as shown in FIG. 1.
The delay bypass circuit for turning off the pulldown transistor element N3 is provided by NMOS bypass transistor element N2 and MOS inverter gate 42 coupled between the control nodes of the secondary pulldown transistor element N1 and the primary pulldown transistor element N3. The delay bypass circuit bypasses the delay resistor RD1 for rapid turn off of N3 during transition from low to high potential at the output V.sub.OUT. Similarly on the supply side, the pullup delay bypass circuit is provided by PMOS bypass transistor element P2 and MOS inverter gate 44 coupled between the control nodes of secondary pullup transistor element P1 and the primary pullup transistor element P3. The supply delay bypass circuit bypasses delay resistor RD2 for rapid turn off of the primary pullup transistor element P3 during transition from high to low potential at the output V.sub.OUT.
A further development for improved edge rate control of the "graduated turn on" or "bifurcated turn on" type output buffer circuits illustrated in U.S. Pat. No. 4,961,010 is described in the Jeffrey B. Davis U.S. Pat. No. 5,036,222 issued Jul. 30, 1991 for OUTPUT BUFFER CIRCUIT WITH OUTPUT VOLTAGE SENSING FOR REDUCING SWITCHING INDUCED NOISE. An output buffer circuit 40a from U.S. Pat. No. 5,036,222 is shown in FIG. 2. An output voltage sensing pulldown control active switching circuit is coupled in series between the control terminal leads of the secondary and primary pulldown transistor elements N1,N3 instead of the passive delay resistor element RD1 of FIG. 1. The pulldown control active switching circuit is provided by the PMOS switch transistor element P4.
For a transition from high to low potential at the output V.sub.OUT, a high potential signal appears at the control gate node of secondary pulldown transistor element N1. N1 turns on to initiate the relatively small sinking current to begin discharging the output load capacitance. The control gate node of the output voltage sensing switch transistor element P4 senses and follows the fall in voltage at the output V.sub.OUT. When the voltage at the output drops by the turn on threshold voltage difference for transistor element P4, pulldown control transistor element P4 switches on, passing the high potential level signal to the gate of primary pulldown transistor element N3. Primary pulldown transistor element N3 conducts, completing discharge of the output load capacitance.
Sinking of current from the output and discharge of the output load capacitance is thus accomplished in two steps. The bifurcated turn on produces two ground bounce events at half the amplitude of conventional ground rise noise spikes. Using the active pulldown control switch transistor element P4 in the circuit of FIG. 2 achieves edge control with greater speed than the passive delay resistor element RD1 of the circuit of FIG. 1.
Similarly, on the power supply side of the output buffer circuit 40a of FIG. 2, an output voltage sensing pullup control active switching circuit is coupled in series between the control nodes of the secondary and primary pullup transistor elements P1,P3. The output voltage sensing pullup control switching circuit is provided by NMOS switch transistor element N4. In the case of a low to high potential transition at the output V.sub.OUT, a low potential signal arrives at the control gate node of secondary pullup transistor element P1. Transistor element P1 turns on initiating the relatively small sourcing current to begin charging the output load capacitance.
The control gate node of output voltage sensing transistor element N4 is coupled to the output V.sub.OUT and senses and follows the rise in voltage at the output. When the voltage rise at the output equals the turn on threshold voltage difference for transistor element N4, N4 switches on passing the low potential signal to the control gate node of primary pullup transistor element P3. Primary pullup transistor element P3 completes charging of output load capacitance with the relatively large sourcing current. The low to high transition at the output is therefore accomplished in two steps with bifurcated turn on of the output pullup transistor elements and with two corresponding V.sub.CC droop events with noise peaks half that of conventional circuits. Using the pullup control active switching transistor element N4 in the circuit of FIG. 2 achieves edge control with greater speed than the passive delay resistor element RD2 of the output buffer circuit of FIG. 1.
Other variations of the pulldown and pullup edge control active switching circuits are described in U.S. Pat. No. 5,036,222. For example the output voltage sensing pulldown control active switch transistor element P4 may be coupled in parallel with the pulldown delay resistor element RD1 between the control nodes of the secondary and primary pulldown transistor elements N1, N3. Similarly on the supply side, the output voltage sensing pullup control active switch transistor element N4 may be coupled in parallel with the passive delay resistor element RD2 between the control nodes of the secondary and primary pullup transistor elements P1,P3.
These and other alternative prior art passive and active delay circuit arrangements for edge control of a high to low transition on the ground power rail side such as an edge controlled bifurcated turn on output buffer circuit are summarized generically in the circuit of FIG. 3 by the circuit block designated DELAY1. The intermediate and predriver circuit elements for example of FIGS. 1 and 2 are summarized in the circuit block designated PREDRIVER CIRCUIT. Furthermore, an output LOAD coupled to the output V.sub.OUT is represented by the load capacitance CL and load resistance RL.
A further anti-noise circuit feature for reducing ground undershoot in an output buffer circuit is illustrated in FIG. 3. This anti-undershoot circuit of FIG. 3 and variations of the anti-undershoot circuit are described in the Alan C. Rogers U.S. Pat. No. 5,049,763 issued Sep. 17, 1991 for ANTI-NOISE CIRCUITS and the Craig M. Peterson U.S. Pat. application Ser. No. 615,077, filed Nov. 19, 1990 for HIGH SPEED ANTI-UNDERSHOOT AND ANTI-OVERSHOOT CIRCUIT. The various anti-undershoot circuit embodiments incorporate an anti-undershoot circuit transistor element AUCT having the primary current path source and drain nodes coupled in an anti-undershoot circuit between a current source such as power supply V.sub.CC and the output ground lead through the output ground parasitic lead inductance LG to the external ground GND. In the example of the circuit of FIG. 3 this coupling of the transistor element AUCT to ground is accomplished through the output V.sub.OUT and the primary pulldown transistor element N3.
The AUCT CONTROL CIRCUIT is constructed for establishing transient flow of a sacrificial current through the AUCT primary current path from power supply V.sub.CC through the output ground lead inductance LG to external ground GND following transition from high to low potential at the output. The primary pulldown transistor element N3 is then conducting. The AUCT parameters and dimensions including channel width and channel resistance are constructed to provide selected resistance in the primary AUCT current path. The anti-undershoot circuit transistor AUCT therefore dissipates undershoot electrical energy stored in the output ground lead inductance LG. This energy dissipation dampens ground potential undershoot and subsequent ringing in the output ground rail.
U.S. Pat. No. 5,049,763 describes a number of different AUCT CONTROL CIRCUITS. According to one embodiment the AUCT CONTROL CIRCUIT is an undershoot detector circuit which generates a transient ground undershoot signal during the transient occurrence of undershoot of potential in the output ground relative to a quiet ground in excess of a selected threshold level. The ground undershoot signal is coupled to the AUCT control node for causing transient flow of sacrificial current through the channel resistance of the AUCT primary current path upon occurrence of ground undershoot. Electrical energy stored in the output ground lead parasitic inductance LG is therefore dissipated during transient occurrence of ground undershoot.
According to another circuit embodiment of the AUCT CONTROL CIRCUIT, a control path resistor element is coupled in series between the control gate node of the primary pullup transistor element P3 and the control gate node of the AUCT. As result the AUCT operates substantially in parallel with the primary pullup transistor element P3 but with transient delay in turn off of the AUCT caused by the control path resistor. The prolonged conduction by the AUCT follows transition from high to low potential at the output and constitutes the transient sacrificial current flow from power supply V.sub.CC. In all of the embodiments, additional current is drawn from the power supply V.sub.CC for undershoot correction. Operation of the anti-undershoot circuit therefore requires increased power dissipation.